Memory efficient JPEG 2000 architecture with stripe pipeline scheme
Resource
Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP '05). IEEE International Conference on
Journal
ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Journal Volume
V
Pages
V1-V4
Date Issued
2005
Author(s)
Abstract
Memory issue is the most critical problem for a high performance JPEG 2000 architecture. The tile memory occupies more than 50% of area in conventional JPEG 2000 architectures. To solve this problem, we propose a stripe pipeline scheme. For this scheme, a Level Switch Discrete Wavelet Transform (LS-DWT) and a Code-block Switch Embedded Block Coding (CS-EBC) are proposed. With small additional memory, the LS-DWT and the CS-EBC can process multiple levels and code-blocks in parallel by an inter-leaved scheme. As a result of above techniques, the overall memory requirements of the proposed architecture can be reduced to only 8.5% comparing with conventional architectures. © 2005 IEEE.
Event(s)
2005 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '05
SDGs
Other Subjects
Data storage equipment; Embedded systems; Pipeline processing systems; Problem solving; Signal encoding; Wavelet transforms; Embedded Block Coding; Level Switch Discrete Wavelet Transform (LS-DWT); Memory efficient JPEG 2000 architecture; Stripe pipeline scheme; Computer architecture
Type
conference paper
File(s)![Thumbnail Image]()
Loading...
Name
01416225.pdf
Size
592.77 KB
Format
Adobe PDF
Checksum
(MD5):51a741b1430b69e83ee42dfe57464b7d