Automatic Test Program Generation for Transition Delay Faults in Pipelined Processors
Journal
Proceedings - 2021 IEEE International Test Conference in Asia, ITC-Asia 2021
ISBN
9781665413343
Date Issued
2021-01-01
Author(s)
Abstract
For processor cores, software-based self-test (SBST) is a promising complement to scan-based testing, especially for applications that demand high reliability. However, most prior SBST techniques only target stuck-at faults and thus fall short in detecting aging induced timing violations. In this paper, we propose an automatic test program generator for detection of transition delay faults (TDFs) in pipelined processors. The key technique is the conversion of scan-based launch-on-capture (LoC) TDF test patterns to instruction sequences, which are combined to form the self-test program. In the field, the processor under test can execute the test program on demand, in its functional mode, to detect TDFs. To facilitate the pattern-to-instruction conversion, a test program template is developed. Derived from the pipelined processor operation, the template helps systematically and efficiently set the flip-flop values specified in LoC test patterns. The proposed technique is validated on a MIPS32 processor and achieves 97.82% transition delay fault coverage.
Subjects
aging | reliability | software-based self-test | test program generation | transition delay fault
Type
conference paper