CSER: BISER-based concurrent soft-error resilience
Journal
VLSI Test Symposium (VTS)
Date Issued
2010-04
Author(s)
Laung-Terng Wang
Touba, N.A.
Zhigang Jiang
Shianling Wu
Jiun-Lang Huang
Abstract
This paper presents a concurrent soft-error resilience (CSER) scheme with features that aid manufacturing test, online debug, and defect tolerance. The proposed CSER scheme is based on the built-in soft-error resilience (BISER) technique. A BISER cell is redesigned into various robust CSER cells that provide slow-speed snapshot, manufacturing test, slow-speed signature analysis, and defect tolerance capabilities. The cell-level area, power, and performance overhead of the robust CSER cells were found to be generally within 1% to 22% of the BISER cell.
Type
conference paper