A BIST scheme for on-chip ADC and DAC testing
Journal
Proceedings -Design, Automation and Test in Europe, DATE
Pages
216-220
Date Issued
2000
Author(s)
Abstract
In this paper we present a BIST scheme for testing on-chip A/D and D/A converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measuring the DNL and INL of the converters. We validate the scheme with software simulation-5% LSB (least significant bit) test accuracy can be achieved in the presence of reasonable analog imperfection.
Type
conference paper