Quantized Neural Network Synthesis for Direct Logic Circuit Implementation
Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal Volume
42
Journal Issue
2
Pages
473
Date Issued
2023-02-01
Author(s)
Abstract
Hardware acceleration enables neural network (NN) inferencing on edge devices and for high throughput applications. Most approaches use neural processing elements for computation while storing weights in memory blocks. To avoid costly memory access, recent efforts seek direct logic implementation with weights hardwired into the circuit. However, special training strategies are often needed, and they could not maintain accuracy. In contrast, we take a trained and quantized NN as input and synthesize it by Booth encoding and logic sharing, resulting in a hardware accelerator without degrading accuracy. Experiments demonstrate that our method outperforms existing work in area reduction and/or throughput and power efficiency.
Subjects
AI accelerators | circuit synthesis | field programmable gate arrays | neural network (NN) hardware
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Type
journal article