https://scholars.lib.ntu.edu.tw/handle/123456789/630383
標題: | Quantized Neural Network Synthesis for Direct Logic Circuit Implementation | 作者: | Huang, Yu Shan JIE-HONG JIANG Mishchenko, Alan |
關鍵字: | AI accelerators | circuit synthesis | field programmable gate arrays | neural network (NN) hardware | 公開日期: | 1-二月-2023 | 出版社: | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | 卷: | 42 | 期: | 2 | 起(迄)頁: | 473 | 來源出版物: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 摘要: | Hardware acceleration enables neural network (NN) inferencing on edge devices and for high throughput applications. Most approaches use neural processing elements for computation while storing weights in memory blocks. To avoid costly memory access, recent efforts seek direct logic implementation with weights hardwired into the circuit. However, special training strategies are often needed, and they could not maintain accuracy. In contrast, we take a trained and quantized NN as input and synthesize it by Booth encoding and logic sharing, resulting in a hardware accelerator without degrading accuracy. Experiments demonstrate that our method outperforms existing work in area reduction and/or throughput and power efficiency. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/630383 | ISSN: | 02780070 | DOI: | 10.1109/TCAD.2022.3183547 |
顯示於: | 電機工程學系 |
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