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  4. Radix-2k Viterbi decoding with transpose path metric processor
 
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Radix-2k Viterbi decoding with transpose path metric processor

Resource
Circuits and Systems, 1994. APCCAS '94., 1994 IEEE Asia-Pacific Conference on
Journal
IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings
Pages
194 - 199
Date Issued
1994-12
Date
1994-12
Author(s)
Lee, Wen-Ta
Chen, Thou-Ho
LIANG-GEE CHEN  
DOI
10.1109/APCCAS.1994.514548
DOI
N/A
URI
http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032410
https://www.scopus.com/inward/record.uri?eid=2-s2.0-0028739717&partnerID=40&md5=fe1800af4fc0d0338690f4bd0248300f
Abstract
In this paper, we present a radix-2k Viterbi decoding with Transpose Path Metric (TPM) processor. The TPM processor can provide a permutation function for state rearrangement with simple local interconnection. For interconnection realization, the routing complexity is less than that of the delay-commutator reported previously. In addition, a higher memory length Viterbi processor can be constructed with lower radix-2k modules. With features of modulation and cell regularity, the radix-2k Viterbi decoding with TPM processor is very suitable for VLSI implementation.
Other Subjects
Algorithms; Computational complexity; Graph theory; Iterative methods; Trellis codes; VLSI circuits; Add compare select; Transpose path metric processor; Trellis diagram; Viterbi decoding; Decoding
Publisher
Proceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems
Type
conference paper
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