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  4. Chamber-to-Chamber Discrepancy Detection in Semiconductor Manufacturing
 
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Chamber-to-Chamber Discrepancy Detection in Semiconductor Manufacturing

Journal
IEEE Transactions on Semiconductor Manufacturing
Journal Volume
33
Journal Issue
1
Pages
86
Date Issued
2020
Author(s)
Aabir Chouichi
JAKEY BLUE  
Claude Yugma
Francois Pasqualini
DOI
68362312
10.1109/TSM.2020.2965288
URI
https://scholars.lib.ntu.edu.tw/handle/123456789/469953
URL
https://doi.org/10.1109/TSM.2020.2965288
Abstract
© 1988-2012 IEEE. For reasons of productivity and throughput maximization, semiconductor equipment suppliers provide multiple-chamber machines to allow the split of production runs over parallel chambers. These latter are expected to perform identically and fabricate similar product quality, which is not usually the case given the low margin of error allowed in the complex manufacturing environment. The difficulty lies in achieving desired yields and controlling the process variability to accurately match the performance of those parallel chambers at all production steps. In this paper, a methodology to detect the mismatching chambers and to identify the root causes integrating all the sources of production data, such as the sensor data and product measurements, is proposed. The Partial Least Squares Discriminant Analysis is employed to separate clusters with high probability density based on classified samples, while providing key variables that most separate the known classes. The supervised classification method, applied to the summarized Fault Detection and Classification data, is followed by the analysis of temporal variables. The proposed approach will be validated with the real practices in an IC fabrication company.
Subjects
Chamber matching; fault detection and classification (FDC); partial least squares discriminant analysis (PLS-DA); wafer metrology
Publisher
Institute of Electrical and Electronics Engineers ({IEEE})
Type
journal article

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