A period tracking based on-chip sinusoidal jitter extraction technique
Resource
VLSI Test Symposium, 2006. Proceedings. 24th IEEE
Journal
Proceedings of the IEEE VLSI Test Symposium
Journal Volume
2006
Pages
400 - 405
Date Issued
2006-04
Author(s)
C.-Y. Kuo
Abstract
In this paper, an on-chip sinusoidal jitter extraction technique based on period tracking is presented. The proposed technique is a viable on-chip solution. It utilizes a variable delay line and a phase comparator to track the signal's cycle lengths without external reference. Digital signal processing techniques are then applied to the obtained signal period sequence to derive the amplitudes and frequencies of the sinusoidal jitter components. Numerical simulations are performed to validate the idea. The results show that the proposed approach can achieve high amplitude and frequency estimation accuracy and is robust in the presence of random jitter components and delay line variations. © 2006 IEEE.
Event(s)
24th IEEE VLSI Test Symposium
Subjects
Built-in self-diagnosis; Built-in self-test; Jitter decomposition; Sinusoidal jitter
Other Subjects
Built-in self test; Computer simulation; Digital signal processing; Electric delay lines; Jitter; Built-in self-diagnosis; Jitter decomposition; Sinusoidal jitter; Chip scale packages
Type
conference paper
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