An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC–DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS
Journal
IEEE Journal of Solid-State Circuits
Date Issued
2023-01-01
Author(s)
Abstract
This article presents an energy-efficient microprocessor design that fully integrates an error-resilient RISC-V core and an embedded dc–dc switched-capacitor voltage regulator (SCVR). The proposed design achieves high energy efficiency, high computation performance, and a small system footprint through several innovations. First, in situ error detection and correction (EDAC) flip-flops (FFs) and an error-resilient static random access memory (SRAM) interfacing technique enable error resilience on the microprocessor without any post-silicon calibration requirement. Next, a fully integrated SCVR featuring a multi-rate successive approximation (MRSA) algorithm and a dynamic conduction loss minimization technique is proposed to achieve high conversion efficiency, high-power density, and fast load regulation. A prototype chip that fully integrates the techniques described above was fabricated in the 28-nm standard CMOS technology with an active area of 0.42 mm $^{2}$ . The measurement results show that the proposed in situ EDAC effectively minimizes the timing margin without any post-silicon calibration to achieve a high-processor performance of 43 MHz with an energy-delay-product (EDP) of 0.57 $\text{pJ}\cdot\mu$ s, showing the state-of-the-art performance and energy efficiency in the standard CMOS technology.
Subjects
Energy efficiency | Error detection and correction (EDAC) | error resilience | fully integrated dc–dc voltage converter | high energy efficiency | microprocessor | Microprocessors | near-threshold voltage (NTV) | Random access memory | Regulation | Regulators | RISC-V | sub-threshold voltage | Timing | Voltage control | voltage regulator
Type
journal article