https://scholars.lib.ntu.edu.tw/handle/123456789/634887
標題: | An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC–DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS | 作者: | Wu, Bing Chen WEI-TING CHEN TSUNG-TE LIU |
關鍵字: | Energy efficiency | Error detection and correction (EDAC) | error resilience | fully integrated dc–dc voltage converter | high energy efficiency | microprocessor | Microprocessors | near-threshold voltage (NTV) | Random access memory | Regulation | Regulators | RISC-V | sub-threshold voltage | Timing | Voltage control | voltage regulator | 公開日期: | 1-一月-2023 | 來源出版物: | IEEE Journal of Solid-State Circuits | 摘要: | This article presents an energy-efficient microprocessor design that fully integrates an error-resilient RISC-V core and an embedded dc–dc switched-capacitor voltage regulator (SCVR). The proposed design achieves high energy efficiency, high computation performance, and a small system footprint through several innovations. First, in situ error detection and correction (EDAC) flip-flops (FFs) and an error-resilient static random access memory (SRAM) interfacing technique enable error resilience on the microprocessor without any post-silicon calibration requirement. Next, a fully integrated SCVR featuring a multi-rate successive approximation (MRSA) algorithm and a dynamic conduction loss minimization technique is proposed to achieve high conversion efficiency, high-power density, and fast load regulation. A prototype chip that fully integrates the techniques described above was fabricated in the 28-nm standard CMOS technology with an active area of 0.42 mm |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/634887 | ISSN: | 00189200 | DOI: | 10.1109/JSSC.2023.3287360 |
顯示於: | 電機工程學系 |
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