Test Clock Domain Optimization to Avoid Scan Shift Failures due to Flip-flop Simultaneous Triggering
Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal Volume
32
Journal Issue
4
Pages
644 - 652
Date Issued
2013-01
Author(s)
Y. C. Huang
M. H. Tsai
W. S. Ding
J. C. M. Li
M. T. Chang
M. H. Tsai
C. M. Tseng
H. C. Li
Abstract
This paper presents a design for testability technique to avoid scan shift failure due to flip-flop simultaneous triggering. The proposed technique changes test clock domains of flip-flops in the regions where severe IR-drop problems occur. A massive parallel algorithm using a graphic processor unit is adopted to speed up the IR-drop simulation during optimization. The experimental data on large benchmark circuits show that peak IR-drop values are reduced by 15% on average compared with the circuit after simple MD-SCAN partition. Our proposed technique quickly optimizes a half-million-gate design within two hours.
Type
journal article