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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Halo profile engineering to reduce Vt fluctuation in high-K/metal-gate nMOSFET
Details
Halo profile engineering to reduce Vt fluctuation in high-K/metal-gate nMOSFET
Journal
International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Pages
145-148
Date Issued
2010
Author(s)
CHEE-WEE LIU
Chen, W.-Y.
Yu, T.-H.
Ohtou, T.
Sheu, Y.-M.
Wu, J.
CHEE-WEE LIU
DOI
10.1109/SISPAD.2010.5604546
URI
http://www.scopus.com/inward/record.url?eid=2-s2.0-78649534792&partnerID=MN8TOARS
http://scholars.lib.ntu.edu.tw/handle/123456789/358251
Type
conference paper
