Spur-suppression techniques for frequency synthesizers
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
54
Journal Issue
8
Pages
653-657
Date Issued
2007-08
Author(s)
Abstract
A frequency synthesizer with two spur-suppression circuits has been fabricated in 0.18 um CMOS technology. The chip area is 1.3 mm x 1.3 mm. The frequency synthesizer consumes 18.9 mW from a 1.8-V supply. Compared with the conventional frequency synthesizer without the spur-suppression circuit, the measured reference spur at 8 MHz is reduced by 18 dBc for the first spur-suppression circuit and 31 dBc for the second one. The measured switching time from 1792 to 1824 MHz is 27.89 us within 20 ppm of the target frequency. © 2007, IEEE. All Rights Reserved.
Other Subjects
CMOS integrated circuits; Interference suppression; Spurious signal noise; Charge pump (CP); Spur-suppression circuit; Frequency synthesizers
Type
journal article