https://scholars.lib.ntu.edu.tw/handle/123456789/333721
標題: | Spur-suppression techniques for frequency synthesizers | 作者: | Che-Fu Liang Hsin-Hua Chen SHEN-IUAN LIU |
公開日期: | 八月-2007 | 卷: | 54 | 期: | 8 | 起(迄)頁: | 653-657 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | A frequency synthesizer with two spur-suppression circuits has been fabricated in 0.18 um CMOS technology. The chip area is 1.3 mm x 1.3 mm. The frequency synthesizer consumes 18.9 mW from a 1.8-V supply. Compared with the conventional frequency synthesizer without the spur-suppression circuit, the measured reference spur at 8 MHz is reduced by 18 dBc for the first spur-suppression circuit and 31 dBc for the second one. The measured switching time from 1792 to 1824 MHz is 27.89 us within 20 ppm of the target frequency. © 2007, IEEE. All Rights Reserved. |
URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/333721 https://www.scopus.com/inward/record.uri?eid=2-s2.0-34547892241&doi=10.1109%2fTCSII.2007.896938&partnerID=40&md5=c67bc4da5ab4da45420a1f4e8bdaf715 |
ISSN: | 15497747 | DOI: | 10.1109/TCSII.2007.896938 | SDG/關鍵字: | CMOS integrated circuits; Interference suppression; Spurious signal noise; Charge pump (CP); Spur-suppression circuit; Frequency synthesizers |
顯示於: | 電機工程學系 |
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