The M2 hierarchical multiprocessor
Journal
Future Generation Computer Systems
Journal Volume
9
Journal Issue
3
Pages
235-240
Date Issued
1993
Author(s)
Abstract
This paper discusses the design and development of a bus-based hierarchical multiprocessor named M2. The primary design goal of the M2 is to derive a multiprocessor architecture that features much higher degree of scalability than the shared-memory shared-bus architecture to meet the ever increasing processing power demanded by large database/knowledgebase computing and transaction processing. If compared with other hierarchical multiprocessors, the M2 is distinctive in its memory configuration, which is aimed at avoiding severe inter-CPU interference due to page-swapping events. If compared with a group of multiprocessors connected by a local area network, the M2 enjoys higher scalability due to higher bandwidth of the backplane bus. © 1993.
Subjects
distributed memory; Hierarchical multiprocessor, scalability; message-passing; shared-memory shared-bus multiprocessor
Other Subjects
Computer architecture; Design; Distributed computer systems; Hierarchical systems; Distributed memory; Hierarchical multiprocessor; Message passing; Scalability; Shared memory shared bus multiprocessor; Multiprocessing systems
Type
journal article
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