https://scholars.lib.ntu.edu.tw/handle/123456789/484679
標題: | The M2 hierarchical multiprocessor | 作者: | Jinsung Sheu, D. Cheng, C.-Y. Yang, C.-Z. YEN-JEN OYANG |
關鍵字: | distributed memory; Hierarchical multiprocessor, scalability; message-passing; shared-memory shared-bus multiprocessor | 公開日期: | 1993 | 卷: | 9 | 期: | 3 | 起(迄)頁: | 235-240 | 來源出版物: | Future Generation Computer Systems | 摘要: | This paper discusses the design and development of a bus-based hierarchical multiprocessor named M2. The primary design goal of the M2 is to derive a multiprocessor architecture that features much higher degree of scalability than the shared-memory shared-bus architecture to meet the ever increasing processing power demanded by large database/knowledgebase computing and transaction processing. If compared with other hierarchical multiprocessors, the M2 is distinctive in its memory configuration, which is aimed at avoiding severe inter-CPU interference due to page-swapping events. If compared with a group of multiprocessors connected by a local area network, the M2 enjoys higher scalability due to higher bandwidth of the backplane bus. © 1993. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/484679 https://www.scopus.com/inward/record.uri?eid=2-s2.0-0027659776&doi=10.1016%2f0167-739X%2893%2990014-G&partnerID=40&md5=34e8eb1f7c5167e0d7bc9256355d5165 |
ISSN: | 0167739X | DOI: | 10.1016/0167-739X(93)90014-G | SDG/關鍵字: | Computer architecture; Design; Distributed computer systems; Hierarchical systems; Distributed memory; Hierarchical multiprocessor; Message passing; Scalability; Shared memory shared bus multiprocessor; Multiprocessing systems |
顯示於: | 生醫電子與資訊學研究所 |
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