Design and Implementation of CMOS Wireless Receiver Front-End Circuits for Multi-band/Multi-standard Communication Systems

With the increasing demands on wireless communication devices, the issues of the low-cost and high-level integration are the trend for the implementation of RF front-end system. Many wireless communication standards exist, such as GSM used for personal cellular phone systems; Bluetooth for short-distance connections of different electronic products; UWB and 802.11a/b/g adopted for wireless local area networks (WLANs) and provide high data-rate transmission. It is constructive to integrate RF circuits applied for different wireless communications on a single chip because of their similarities in many wireless transceivers. With the advances in deep submicron fabrication process recently, CMOS technology is showing the potential to meet these requirements. Besides, the high integration ability with baseband analog and digital circuits of CMOS techniques makes it the best choice to achieve the multi-band/multi-standard wireless applications.
Two circuit topologies are utilized to achieve this purpose: concurrent-wideband and tunable circuits. This thesis presents both circuit techniques.
The mixer is used to down-converts the RF signal to low frequency IF signal. A wideband mixer design reports in this thesis with non-uniform artificial transmission lines to construct the input matching network, and modified capacitive degeneration to enhance the bandwidth, the proposed mixer has operation frequency from 2GHz to 28GHz, with 12.5±1 dB conversion gain and IIP3 larger than -2 dBm, and dissipations 40mW with 2V supply voltage.
By the usage of the frequency-selection mechanisms, tunable RF receivers are implemented with different broadband input matching techniques and frequency-tuning techniques. With the proposed transformer composed of the input matching inductors, the LNA has return loss less than -10 dB from 3.5 GHz to 5.0 GHz and provides conversion gain 22.2±2.4 dB with IIP3 larger than -6 dBm from 3.0 to 5.0 GHz bands. The power consumption of the receiver is 40mW with a 2V supply voltage.
The second RF receiver uses a common-gate architecture LNA and modified tunable multi-resonant tuned load. A stacked inductor adopted as the RF chock at the input port of the LNA provides high inductance with smaller chip area and shorter metal line to reduce the ohmic loss of the inductor. A modified DC bias technique for the double- quadrature mixer can enhance the linearity performance. The flicker noise is also suppressed by utilizing pMOSFETs for the mixer and the IF amplifiers. The IF amplifiers are designed to enhance the dynamic range of the receiver and the receiver can be more suitable for different wireless system applications.