Test-Clock Domain Optimization for Peak Power-Supply Noise Reduction During Scan
Journal
International Test Conference
Date Issued
2011-01
Author(s)
R.Y. Wen
Y.C. Huang
M.H. Tsai
K.Y. Liao
J. C.-M. Li
M.-T. Chang
M.-H. Tsai
C.-M. Tseng
H.-C. Li
Abstract
This paper presents a design for testability (DfT) technique to reduce the peak power supply noise (PPSN) during scan chain shifting. The proposed partition technique reduces the maximum flip-flop density that belongs to the same test clock. The experimental data on large benchmark circuits show that IR drop are reduced by 38.7% on the average compared with the circuit before optimization. Our proposed technique quickly optimizes a half million gate design within 14 minutes while the commercial IR drop simulation tool took over 3 hours.
SDGs
Type
conference paper