Systematic Hold-time Fault Diagnosis and Failure Debug in Production Chips
Journal
Proceedings of the Asian Test Symposium
Journal Volume
2020-November
Date Issued
2020
Author(s)
Abstract
Hold-time faults can occur in complex designs but can be difficult to diagnose. This paper presents a systematic hold-time diagnosis method for logic circuits. A four-phase flow is introduced to solve the problem. The identification phase identifies groups of systematic error logs by systematic errors. The filtering phase builds a majority error log to avoid the effect of random defects. The verification phase verifies that the candidate fault is a hold-time fault and recognizes capture flip-flops. The determination phase determines the fault models and their corresponding faulty flip-flops. Experiments on two industrial cases show the effectiveness of our technique, both of which have been verified through root-cause analysis. The proposed technique outperforms standard diagnosis performed by a commercial tool. ? 2020 IEEE.
Subjects
Computer circuits; Flip flop circuits; Commercial tools; Complex designs; Diagnosis methods; Fault model; Four-phase; Hold-time faults; Random defects; Root cause analysis; Systematic errors
Type
conference paper