https://scholars.lib.ntu.edu.tw/handle/123456789/580675
標題: | Systematic Hold-time Fault Diagnosis and Failure Debug in Production Chips | 作者: | Liu C.-Y Wu M.-T Li J.C.-M Bhargava G Nigh C. CHIEN-MO LI |
關鍵字: | Computer circuits; Flip flop circuits; Commercial tools; Complex designs; Diagnosis methods; Fault model; Four-phase; Hold-time faults; Random defects; Root cause analysis; Systematic errors | 公開日期: | 2020 | 卷: | 2020-November | 來源出版物: | Proceedings of the Asian Test Symposium | 摘要: | Hold-time faults can occur in complex designs but can be difficult to diagnose. This paper presents a systematic hold-time diagnosis method for logic circuits. A four-phase flow is introduced to solve the problem. The identification phase identifies groups of systematic error logs by systematic errors. The filtering phase builds a majority error log to avoid the effect of random defects. The verification phase verifies that the candidate fault is a hold-time fault and recognizes capture flip-flops. The determination phase determines the fault models and their corresponding faulty flip-flops. Experiments on two industrial cases show the effectiveness of our technique, both of which have been verified through root-cause analysis. The proposed technique outperforms standard diagnosis performed by a commercial tool. ? 2020 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85099145446&doi=10.1109%2fATS49688.2020.9301504&partnerID=40&md5=a18a68a70a67c4ecd279f2b455884000 https://scholars.lib.ntu.edu.tw/handle/123456789/580675 |
ISSN: | 10817735 | DOI: | 10.1109/ATS49688.2020.9301504 |
顯示於: | 電機工程學系 |
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