Analysis of subthreshold swing and internal voltage amplification for hysteresis-free negative capacitance FinFETs
Journal
2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings
Pages
134-135
Date Issued
2017
Author(s)
Chiu P.-C
Abstract
We present the device design guideline for hysteresis-free negative capacitance FinFETs (NC-FinFETs) to enhance the internal voltage amplification (Av) and reduce the subthreshold swing (SS). Av can be increased by increasing fin width (Wfin), coercive field (Ec), and thickness of the ferroelectric layer (Tfe), and Ay can also be enhanced by reducing EOT, channel length (Lch), buried oxide thickness (Tbox), fin height (Hfin) and remnant polarization (P0). The subthreshold swing improvements of NC-FinFETs over FinFETs become larger as AV increases. With the same channel length, compared with the NC-FinFET without underlap design, NC-FinFET with underlap design exhibits better capacitance matching and larger AV, hence showing larger subthreshold swing improvement and on-current improvement over FinFET. At shorter Lch (= 12.5nm), NC-FinFETs with underlap design exhibit 73.6% improvements in intrinsic delay compared with the FinFETs due to its larger effective drive current. ? 2017 IEEE.
Subjects
Capacitance; Electron devices; Ferroelectric materials; Fins (heat exchange); Hysteresis; Manufacture; MOSFET devices; Amplification factors; Buried oxide thickness; Capacitance matching; Ferroelectric layers; Negative capacitance; Remnant polarizations; Sub-threshold swing(ss); Subthreshold swing; FinFET
Type
conference paper