A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta-Sigma Modulator with an Asynchronous Sequential Quantizer and Digital Excess Loop Delay Compensation
Journal
IEEE TCAS-II
Journal Volume
58
Journal Issue
12
Pages
867-871
Date Issued
2011-12
Author(s)
Abstract
A second-order continuous-time delta-sigma modulator incorporating a proposed 4-bit asynchronous sequential quantizer and a digital excess-loop-delay (ELD) compensation technique is presented. The sequential operation of the proposed quantizer facilitates low power consumption while the hardware-efficient digital compensation technique allows the modulator to accommodate ELD. With a 1-MHz bandwidth and a 60-MHz sampling rate, the measured peak signal-to-noise-and-distortion ratio and dynamic range are 62 and 67 dB, respectively. Fabricated in a 90-nm CMOS, this chip consumes only 0.89 mW from a 1.2-V supply. © 2006 IEEE.
Subjects
Asynchronous circuits; Delta-sigma modulator; Digitally assisted design; Excess loop delay (ELD)
Other Subjects
Continuous time systems; Delay circuits; Delta sigma modulation; Energy efficiency; Signal to noise ratio; Asynchronous circuits; Compensation techniques; Delta sigma modulator; Digital compensation; Excess loop delays (ELD); Low-power consumption; Sequential operations; Signal to noise and distortion ratio; Modulators
Type
journal article