A leakage-compensated PLL in 65-nm CMOS technology
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
56
Journal Issue
7
Pages
525-529
Date Issued
2009
Author(s)
Hung, C.-C.
Abstract
A leakage compensation technique is presented to compensate the on-chip loop filter leakage for phase-locked loops in 65-nm complementary metal-oxide-semiconductor technology. Using the leakage compensation technique, the measured root-mean-square jitter is reduced to 3.10 ps when the output frequency is 950 MHz. This chip consumes 10 mW, and the active area is 0.14 mm2. © 2009 IEEE.
Subjects
Leakage compensation; Nanoscale CMOS; Phase-locked loop
SDGs
Other Subjects
Metals; MOS devices; Oxide semiconductors; Phase locked loops; Semiconductor device manufacture; Active area; CMOS technology; Complementary metal-oxide-semiconductor technologies; Leakage compensation; Loop filter; Nano-scale CMOS; Output frequency; Root mean square jitter; CMOS integrated circuits
Type
journal article