https://scholars.lib.ntu.edu.tw/handle/123456789/499881
標題: | A leakage-compensated PLL in 65-nm CMOS technology | 作者: | Hung, C.-C. SHEN-IUAN LIU |
關鍵字: | Leakage compensation; Nanoscale CMOS; Phase-locked loop | 公開日期: | 2009 | 卷: | 56 | 期: | 7 | 起(迄)頁: | 525-529 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | A leakage compensation technique is presented to compensate the on-chip loop filter leakage for phase-locked loops in 65-nm complementary metal-oxide-semiconductor technology. Using the leakage compensation technique, the measured root-mean-square jitter is reduced to 3.10 ps when the output frequency is 950 MHz. This chip consumes 10 mW, and the active area is 0.14 mm2. © 2009 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/499881 https://www.scopus.com/inward/record.uri?eid=2-s2.0-68249144764&doi=10.1109%2fTCSII.2009.2020948&partnerID=40&md5=79b4071c3dec8898329f928388a5f42d |
ISSN: | 15497747 | DOI: | 10.1109/TCSII.2009.2020948 | SDG/關鍵字: | Metals; MOS devices; Oxide semiconductors; Phase locked loops; Semiconductor device manufacture; Active area; CMOS technology; Complementary metal-oxide-semiconductor technologies; Leakage compensation; Loop filter; Nano-scale CMOS; Output frequency; Root mean square jitter; CMOS integrated circuits |
顯示於: | 電機工程學系 |
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