A broadband chip-level power-bus model feasible for power integrity chip-package co-design in high-speed memory circuits
Journal
IEEE Transactions on Electromagnetic Compatibility
Journal Volume
52
Journal Issue
1
Pages
235-239
Date Issued
2010-02
Author(s)
Abstract
Based on two-port measurements, a distributed compact model and an extraction method for the power bus of a high-speed memory chip are proposed. The 1-D model is constructed according to the relative locations of the power and ground pads on the chip. The power bus around each power or ground pad is modeled by a section of resistor-inductor-capacitor (RLC) T-model, and the complete distributed model is formed by cascading all the T-model sections. The T-model at each section can be extracted through the measured two-port Z-parameters by using the Powell's optimization method. Because the model is extracted from measured data, detailed (or proprietary) chip-layout information is not necessary. Another advantage is this compact model keeps the broadband accuracy by the distribution concept and is easy to link with the package model for the power integrity codesign.
SDGs
Type
journal article