Gate Misalignment Effect Related Capacitance Behavior of a 100nm DG FD SOI NMOS Device with n+/p+ Poly Top/Bottom Gate
Journal
IEEE Conference on Electron Devices and Solid-State Circuits
Pages
397-400
Date Issued
2004-10
Author(s)
Abstract
This paper reports the gate-misalignment-effect related capacitance behavior of a 100nm double-gate (DG) fully-depleted (FD) SOI NMOS device with the n + p + poly top/bottom gate. Based on the 2D simulation result, with the gate misalignment, the sudden fall in the gate-drain/source capacitance (C GD /C GS ) of the device at V G =0.5V is mitigated due to the reduced hole accumulation/ depletion in the bottom channel controlled by the p + bottom gate with the increased fringing electric field effect.
Type
conference paper