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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Enhanced power and signal integrity through layout optimization of high-speed memory systems
Details
Enhanced power and signal integrity through layout optimization of high-speed memory systems
Journal
IEEE Electrical Design of Advanced Packaging and Systems Symposium
Journal Volume
2019-December
Date Issued
2019
Author(s)
Weng, P.-Y.
Cheng, C.-H.
Wu, T.-L.
Chen, C.-H.
Chen, J.
Kuo, E.
Liao, C.-L.
Mutnury, B.
TZONG-LIN WU
DOI
10.1109/EDAPS47854.2019.9011625
URI
https://www.scopus.com/inward/record.url?eid=2-s2.0-85085060784&partnerID=40&md5=d2d243d8b127d3b421138f45e788f002
https://scholars.lib.ntu.edu.tw/handle/123456789/559277
Type
conference paper