Enhanced power and signal integrity through layout optimization of high-speed memory systems
Journal
IEEE Electrical Design of Advanced Packaging and Systems Symposium
Journal Volume
2019-December
Date Issued
2019
Author(s)
Abstract
In this paper, a high-speed memory bus with non-ideal power/ground reference was analyzed. Noise from power planes and vias would couple to the double-data-rate (DDR) signals and impact signal quality. Several design parameters of the system structure were considered to improve the DDR signal quality. Parameters such as location of the signals, location of noise source and placement of decoupling capacitor are considered to reduce the noise coupling. With optimized parameters, the transfer impedance between the victim signal and noise source could be suppressed and the noise coupling can be reduced accordingly. Time domain eye-diagram plots of the DDR signal are also used to depict the signal quality.
Type
conference paper