Skip to main content
English
中文
Log In
Log in
Log in with ORCID
NTU Single Sign On
Have you forgotten your password?
Home
College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
An On-Chip Random Jitter Testing Technique Using Low Tap-Count Delay Lines
Details
An On-Chip Random Jitter Testing Technique Using Low Tap-Count Delay Lines
Journal
International Mixed-Signal Testing Workshop
Date Issued
2005-06
Author(s)
JIUN-LANG HUANG
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/318009
Type
conference paper
