Simultaneous routing and buffering in floorplan design
Journal
International Symposium on VLSI Technology, Systems, and Applications
Journal Volume
2003-January
Pages
188-191
Date Issued
2003
Author(s)
Abstract
To deal with the floorplan design in a System-on-a-Chip (SOC), we have developed an EDA tool that simultaneuosly considers the problems of routing and buffer-insertion in floorplanning. This routing and buffering tool mainly contains a Manhattan routing (MR) algorithm and a maze-based between-buffer routing (MBR) algorithm. Since the processing speed of its MR is very fast, this tool can be integrated into an iterative floorplanning algorithm to promote the routability of a floorplan solution. © 2003 IEEE.
Subjects
Buffer insertion; Floorptanning; Global routing
Other Subjects
Algorithms; Application specific integrated circuits; Buffer circuits; Iterative methods; Programmable logic controllers; System-on-chip; Buffer insertion; Floor-planning; Floorplan design; Floorptanning; Global routing; Manhattan routing; Processing speed; System on a chip; Integrated circuit design
Type
conference paper
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