Implementation of programmable delay lines on off-the-shelf FPGAs
Journal
IEEE AUTOTESTCON
Pages
37-40
Date Issued
2013-09
Author(s)
Abstract
The programmable delay line is a key component in test and measurement applications; it facilitates key functionalities such as de-skewing, timing adjustment, edge placement, and time-to-digital conversions. In this work, we investigate the implementation of programmable delay lines on off-the-shelf FPGAs (field programmable gate array). Two flavors of delay lines, coarse and fine, are realized and the corresponding step sizes are 105 and 13 ps, respectively.
Type
conference paper