RLC coupling-aware simulation and on-chip bus encoding for delay reduction
Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal Volume
25
Journal Issue
10
Pages
2258-2264
Date Issued
2006
Author(s)
Abstract
This paper shows that the worst case switching pattern that incurs the longest bus delay while considering the RLC effect is quite different from that while considering the RC effect alone. It implies that the existing encoding schemes based on the RC model may not improve or possibly worsen the delay when the inductance effects become dominant. A bus-invert method is also proposed to reduce the on-chip bus delay based on the RLC model. Simulation results show that the proposed encoding scheme significantly reduces the worst case coupling delay of the inductance-dominated buses. © 2006 IEEE.
Subjects
Bus-invert method; Coupling; Inductance; Interconnect delay; Worst case switching pattern
Other Subjects
Capacitance; Computer simulation; Delay circuits; Electric resistance; Encoding (symbols); Inductance; Mathematical models; Microprocessor chips; Switching theory; Bus-invert method; Inductance-dominated buses; Interconnect delay; Worst case switching pattern; Coupled circuits
Type
journal article
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