https://scholars.lib.ntu.edu.tw/handle/123456789/147601
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor | National Taiwan University Dept Elect Engn | en |
dc.contributor.author | Chen, Chien-Chung | en |
dc.contributor.author | Kuo, James B. | en |
dc.contributor.author | Su, Ke-Wei | en |
dc.contributor.author | Liu, Sally | en |
dc.creator | Chen, Chien-Chung; Kuo, James B.; Su, Ke-Wei; Liu, Sally | - |
dc.date | 2006-10 | - |
dc.date.accessioned | 2006-11-14T18:13:51Z | - |
dc.date.accessioned | 2018-07-06T09:34:45Z | - |
dc.date.available | 2006-11-14T18:13:51Z | - |
dc.date.available | 2018-07-06T09:34:45Z | - |
dc.date.issued | 2006-10 | - |
dc.identifier | 246246/200611150121241 | zh_TW |
dc.identifier.uri | http://ntur.lib.ntu.edu.tw//handle/246246/200611150121241 | - |
dc.description.abstract | This paper reports an analysis of the gate–source/ drain capacitance behavior of a narrow-channel fully depleted (FD) silicon-on-insulator (SOI) NMOS device considering the three-dimensional (3-D) fringing capacitances. Based on the 3-D simulation results, when the width of the FD SOI NMOS device is scaled down to 0.05 μm, the inner-sidewall-oxide fringing capacitance (CFIS), due to the fringing electric field at the edge of the mesa-isolated structure of the FD SOI NMOS device biased at VG = 0.3 V and VD = 1 V, is the second largest contributor to the gate–source capacitance (CGS). Thus, when using nanometer CMOS devices with a channel width smaller than 0.1 μm, CFIS cannot be overlooked for modeling gate–source/drain capacitance (CGS/CGD). | en |
dc.format | application/pdf | zh_TW |
dc.format.extent | 823010 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language | en-US | zh_TW |
dc.language.iso | zh_TW | - |
dc.publisher | Taipei:National Taiwan University Dept Elect Engn | en |
dc.relation | IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 10, OCTOBER 2006 | en |
dc.relation.ispartof | IEEE Transactions on Electron Devices | - |
dc.source | http://ieeexplore.ieee.org/ | en |
dc.subject | Capacitance | en |
dc.subject | CMOSFETs | en |
dc.subject | modeling | en |
dc.subject | silicon-oninsulator (SOI) technology, simulation | en |
dc.title | Analysis of the Gate–Source/Drain Capacitance Behavior of a Narrow-Channel FD SOI NMOS Device Considering the 3-D Fringing Capacitances Using 3-D Simulation | en |
dc.type | journal article | en |
dc.relation.pages | - | - |
dc.relation.journalvolume | VOL. 53 | - |
dc.relation.journalissue | NO. 10 | - |
dc.identifier.uri.fulltext | http://ntur.lib.ntu.edu.tw/bitstream/246246/200611150121241/1/169.pdf | - |
item.languageiso639-1 | zh_TW | - |
item.cerifentitytype | Publications | - |
item.fulltext | with fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.openairetype | journal article | - |
item.grantfulltext | open | - |
crisitem.author.dept | Psychology | - |
crisitem.author.dept | Center for Artificial Intelligence and Advanced Robotics | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.orcid | 0000-0002-3848-0180 | - |
crisitem.author.parentorg | College of Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
顯示於: | 電機工程學系 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。