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  1. NTU Scholars
  2. 電機資訊學院
  3. 電機工程學系

電機工程學系 : [4792/25452] Collection home page

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Collection's Items (Sorted by Title in Ascending order): 1 to 20 of 25452
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Issue DateTitleAuthor(s)SourcescopusWOSFulltext/Archive link
2023A 0.0072-mm<sup>2</sup>10-bit 100-MS/s Calibration-free SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOSTsai, Yao Hung; SHEN-IUAN LIU 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
2023A 0.02mm<sup>2</sup>Sub-Sampling PLL with Spur Reduction Technique in 90nm CMOS TechnologyCheng, Sheng Jen; Qiu, You Rong; Hong, Chung Hung; Liu, Wei Yi; Li, Chia Hsuan; CHUNG-PING CHEN 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
2017A 0.035-pJ/bit/dB 20-Gb/s Adaptive Linear Equalizer with an Adaptation Time of 2.68 μsChen, K.-Y.; Chen, W.-Y.; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs88
2004A 0.1-23-GHz SiGe BiCMOS analog multiplier and mixer based on attenuation-compensation techniqueTsai, Ming-Da; Lin, Chin-Shen; Wang, Chi-Hsueh; Lien, Chun-Hsien; Wang, HueiRadio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE 00
1992A 0.1-W W-band pseudomorphic HEMT MMIC power amplifierChen, T.H.; Tan, K.L.; Dow, G.S.; Wang, H.; Chang, K.W.; Ton, T.N.; Allen, B.; Berenz, J.; Liu, P.H.; Streit, D.; Hayashibara, G.; HUEI WANG GaAs IC Symposium Technical Digest 1992220
2006A 0.18μm probabilistic-based noise-tolerate circuit design and implementation with 28.7dB noise-immunity improvementWey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; Wu, A.-Y.; AN-YEU(ANDY) WU 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006220
20010.24-μm CMOS technology and BSIM RF modeling for bluetooth power applicationsChen, Y.-J.E.; Heo, D.; Laskar, J.; Bien, D.; YI-JAN EMERY CHEN Microwave Journal1
2018A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy HarvestingKai-Ren Cheng; Hsin-Shu Chen; Micka?l Lallart; Wen-Jong Wu; HSIN-SHU CHEN IEEE ISCAS60
2017A 0.3-V 7.6-fJ/conv-step delta-sigma time-to-digital converter with a gated-free ring oscillatorChang, C.-K.; Tsai, Y.-K.; Cheng, K.-H.; Lu, L.-H.; LIANG-HUNG LU Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 201700
2017A 0.31-pJ/bit 20-Gb/s DFE with 1 Discrete Tap and 2 IIR Filters Feedback in 40-nm-LP CMOSChen, K.-Y.; Chen, W.-Y.; SHEN-IUAN LIU IEEE Transactions on Circuits and Systems II: Express Briefs1515
2015A 0.33 V 683 μW K-band transformer-based receiver front-end in 65 nm CMOS technologyCheng, J.-H.; Hsieh, C.-L.; Wu, M.-H.; Tsai, J.-H.; Huang, T.-W.; TIAN-WEI HUANG IEEE Microwave and Wireless Components Letters1211
2015A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOSHsieh, C.-E.; Liu, S.-I.; SHEN-IUAN LIU Proceedings - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014160
2015A 0.43pJ/bit true random number generatorKuan, T.-K.; Chiang, Y.-H.; Liu, S.-I.; SHEN-IUAN LIU Proceedings - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014210
2003A 0.5-14-GHz 10.6-dB CMOS cascode distributed amplifierLiu, Ren-Chieh; Lin, Chin-Shen; Deng, Kuo-Liang; Wang, HueiVLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on 
2007A 0.5-V 1.9-GIk low-power phase-locked loop in 0.18-μm CMOSHsieh, H.-H.; Lu, C.-T.; LIANG-HUNG LU ; LIANG-HUNG LU IEEE Symposium on VLSI Circuits, Digest of Technical Papers370
20090.5-V 5.6-GHz CMOS receiver subsystemChen, H.-C.; Wang, T.; Chiu, H.-W.; Kao, T.-H.; Lu, S.-S.; SHEY-SHI LU IEEE Transactions on Microwave Theory and Techniques 
2020A 0.5-V, 1.79-μW, 250-kbps Wake-up Receiver for IoT application in 90-nm CMOSZhang Z.-C; Chiu C.-Y; Yuan H.-C; TSUNG-HSIEN LIN 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 202020
2018A 0.55THz Y-Vector Network Configured Beam Steering Phased Array in CMOS TechnologyZhao, Y.; Hadi, R.A.; Lu, H.-C.; Tseng, T.-S.; Zhang, Y.; Qiao, W.; Lo, M.K.; Jou, C.-P.; Zhang, K.; Chang, M.-C.F.; HSIN-CHIA LU IEEE MTT-S International Microwave Symposium Digest20
20090.5V SOI CMOS Dual-Threshold Circuit Technique Via DTMOS for Design Optimization of Low-Power VLSI System ApplicationsW. J. H. Lin; C. Y. Chien; J. B. Kuo; JAMES-B KUO EUROSOI 
2019A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI SystemYao-Sheng Hu; Li-Yu Huang; Hsin-Shu Chen; HSIN-SHU CHEN IEEE Journal of Solid-State Circuits45
Collection's Items (Sorted by Title in Ascending order): 1 to 20 of 25452
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臺大位居世界頂尖大學之列,為永久珍藏及向國際展現本校豐碩的研究成果及學術能量,圖書館整合機構典藏(NTUR)與學術庫(AH)不同功能平台,成為臺大學術典藏NTU scholars。期能整合研究能量、促進交流合作、保存學術產出、推廣研究成果。

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