https://scholars.lib.ntu.edu.tw/handle/123456789/148582
標題: | Efficient hybrid tree/linear array architectures for block-matching motion estimation algorithms | 作者: | MIIN-JANG CHEN LIANG-GEE CHEN Cheng, K.-N. Chen, M.C. |
關鍵字: | Motion estimation; Video coding; Videoconferencing | 公開日期: | 八月-1996 | 卷: | 143 | 期: | 4 | 起(迄)頁: | 217 - 222 | 來源出版物: | IEE Proceedings: Vision, Image and Signal Processing | 摘要: | Execution latency and I/O bandwidth play essential roles in determining the effectiveness and the cost of a parallel hardware implementation for block-matching motion estimation algorithms. Unfortunately, almost all traditional architecture designs, e.g. the twodimensional mesh-connected systolic array architecture (2DMCSA), and the tree-type structure (TTS), fail to take these two factors into account simultaneously. As a result, they suffer from either large execution latency or huge input bandwidth requirements. The authors propose a family of tree/linear architectures, which efficiently optimise the total implementation cost by combining the merits of the 2DMCSA and the TTS. Moreover, to facilitate hardware designs, the authors present the tree-cut techniques and the on-chip buffer design method to meet computational demands of various video compression applications. Since the proposed architectures are capable of executing the . exhaustive search and the fast search blockmatching algorithms, they offer relatively flexible and cost-effective hardware solutions for a wide range of video coding systems, including CD-ROM, portable visual communications systems and high-definition TV. © IEE, 1996. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032494 https://www.scopus.com/inward/record.uri?eid=2-s2.0-0030206740&doi=10.1049%2fip-vis%3a19960541&partnerID=40&md5=cb7111e781aabdec192314ac1efbf065 |
ISSN: | 1350245X | 其他識別: | 1350-245X | DOI: | 10.1049/ip-vis:19960541 | SDG/關鍵字: | Algorithms; Bandwidth; CD-ROM; Computer architecture; Computer hardware; Digital signal processing; Estimation; High definition television; Image coding; Image compression; Optimization; Parallel processing systems; Block matching motion estimation algorithms; Fast search block matching algorithms; Hybrid tree linear array architectures; Two dimensional mesh connected systolic arrays architecture; Image communication systems |
顯示於: | 電機工程學系 |
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00537240.pdf | 1.05 MB | Adobe PDF | 檢視/開啟 |
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