DC 欄位 | 值 | 語言 |
dc.contributor | Dept. of Electr. Eng., National Taiwan Univ. | en |
dc.contributor.author | Liu, Tsung-Te | en |
dc.contributor.author | Wang, Chorng-Kuang | en |
dc.creator | Liu, Tsung-Te; Wang, Chorng-Kuang | - |
dc.date | 2004-09 | en |
dc.date.accessioned | 2007-04-19T04:05:22Z | - |
dc.date.accessioned | 2018-07-06T13:11:31Z | - |
dc.date.available | 2007-04-19T04:05:22Z | - |
dc.date.available | 2018-07-06T13:11:31Z | - |
dc.date.issued | 2004-09 | - |
dc.identifier | N/A | en |
dc.identifier.uri | http://ntur.lib.ntu.edu.tw//handle/246246/200704191001707 | - |
dc.format | application/pdf | en |
dc.format.extent | 314405 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language | en-US | en |
dc.language.iso | en_US | - |
dc.relation | Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European | en |
dc.relation.ispartof | 30th European Solid-State Circuits Conference, 2004. ESSCIRC 2004 | - |
dc.title | A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator | en |
dc.type | journal article | en |
dc.identifier.doi | 10.1109/ESSCIR.2004.1356696 | en |
dc.relation.pages | - | - |
dc.identifier.uri.fulltext | http://ntur.lib.ntu.edu.tw/bitstream/246246/200704191001707/1/01356696.pdf | - |
item.fulltext | with fulltext | - |
item.openairetype | journal article | - |
item.languageiso639-1 | en_US | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.grantfulltext | open | - |
item.cerifentitytype | Publications | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.orcid | 0000-0002-5433-9830 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
顯示於: | 電機工程學系
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