DC 欄位 | 值 | 語言 |
dc.contributor | 王勝德 | zh-TW |
dc.contributor | Wang, Sheng-De | en |
dc.contributor | 臺灣大學:電機工程學研究所 | zh-TW |
dc.contributor.author | 翁誌宏 | zh-TW |
dc.contributor.author | Weng, Chih-Hung | en |
dc.creator | 翁誌宏 | zh-TW |
dc.creator | Weng, Chih-Hung | en |
dc.date | 2009 | en |
dc.date.accessioned | 2010-07-01T05:02:59Z | - |
dc.date.accessioned | 2018-07-06T13:13:12Z | - |
dc.date.available | 2010-07-01T05:02:59Z | - |
dc.date.available | 2018-07-06T13:13:12Z | - |
dc.date.issued | 2009 | - |
dc.identifier.other | U0001-0807200923241100 | en |
dc.identifier.uri | http://ntur.lib.ntu.edu.tw//handle/246246/188156 | - |
dc.description.abstract | 在嵌入式系統中,多媒體已變得越來越重要。誠如大家所知,移動估測在視訊壓縮中演重要的角色,由於兩張連續的影像通常差異並不大,尤其在較高的畫面更新率下異更小,所以移動估測藉由利用視訊資料中時間冗餘資訊來達成視訊壓縮。新的編碼標準H.264採用了相當多新的技術。例如為了要能夠在畫面中選擇更合的區塊,H.264採用了可變區塊大小之移動估測,相較於先前的技術,編碼效能大幅提升。然而,H.264的計算複雜度也大幅地增加。在編碼器中的所有技術之中,移動測正是最花時間的功能。尤其是使用軟體的方法來實現。文針對可變區塊大小之移動估測結合了軟體和硬體的最佳化。在軟體最佳化方,我們提出了一個新的演算法,將移動向量分群,以便能夠更有效率的選擇合適的塊。在硬體方面,我們使用了平行化管線的技術來提升效能。我們使用了現場可程化邏輯陣列來實現這個架構。整個電路可以操作在311Mhz,而僅用掉65k的閘。結顯示我們的架構在248Mhz之下可以達到每秒30張1920x1080解析度的16x16全域搜移動估測。就單位面積的產量來看,我們提出的架構可以達到更高的硬體效率。 | zh-TW |
dc.description.abstract | Multimedia has become more and more important in embedded systems. It isell-known that the motion estimation plays an essential role in video coding. Its also the key elements that achieve video compression by exploiting temporaledundancy of video data because the di erence between two successive framesre usually very small, especially for high frame rates.he latest coding standard H.264 has adopted lots of new features. For in-tance, in order to adaptively choose the proper block size for frame macroblock,.264 has used variable block size motion estimation which can signi cantly im-rove the coding performance compared to previous techniques. However, theomputational complexity of H.264 has also increased drastically. Among all theechniques in the encoder, motion estimation is exactly the most time-consumingunction especially when it is implemented in a software approach.n this thesis, we combine software and hardware optimizations for variablelock size motion estimation. At the software level, we propose a new algorithmhat can e ciently select a suitable block size by grouping the motion vectors. Athe hardware level, we propose a pipelined and parallel architecture to enhancehe performance. Our architecture is implemented on an FPGA platform. Itperates at a maximum clock frequency of 311 MHz with gate count 65k. Theesults show that under a frequency of 248MHz, our architecture allows the pro-essing of 1920x1080 at 30fps with full search motion estimation in a 16x16 searchange. This proposed architecture provides a better hardware e ciency in termsf throughput and gate count than previous works. | en |
dc.description.tableofcontents | 1 Introduction 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Background and Problem Analysis 4.1 Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 Color Representations . . . . . . . . . . . . . . . . . . . . . 5.1.2 Transformation . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.3 Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.4 Entropy Coding . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Motion Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 Searching Strategy . . . . . . . . . . . . . . . . . . . . . . . 11.2.2 Matching Criteria . . . . . . . . . . . . . . . . . . . . . . . . 16.2.3 Variable Block Size Motion Estimation . . . . . . . . . . . . 17.3 Complexity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Related Works 21.1 Mode Decision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . 22.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Proposed Method 25.1 Vectors Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.2 Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 30.3 Implementation Platform . . . . . . . . . . . . . . . . . . . . . . . . 34.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Experimental Results 37.1 Synthesis Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37.2 Performance of Proposed Algorithm . . . . . . . . . . . . . . . . . . 38.3 Performance of Proposed Architecture . . . . . . . . . . . . . . . . 38.4 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Conclusion 43.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44ibliography 45 | en |
dc.format.extent | 826498 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language | en | en |
dc.language.iso | en_US | - |
dc.subject | 移動估測 | zh-TW |
dc.subject | 可變區塊大小移動估測 | zh-TW |
dc.subject | 硬體加速 | zh-TW |
dc.subject | Motion Estimation | en |
dc.subject | VBSME | en |
dc.subject | Hardware Accelerator | en |
dc.title | 可變區塊大小之移動估測演算法與硬體架構 | zh-TW |
dc.title | Algorithms and Hardware Architectures for Variable Block Size Motion Estimation | en |
dc.type | thesis | en |
dc.identifier.uri.fulltext | http://ntur.lib.ntu.edu.tw/bitstream/246246/188156/1/ntu-98-R96921075-1.pdf | - |
item.fulltext | with fulltext | - |
item.languageiso639-1 | en_US | - |
item.openairecristype | http://purl.org/coar/resource_type/c_46ec | - |
item.cerifentitytype | Publications | - |
item.openairetype | thesis | - |
item.grantfulltext | open | - |
顯示於: | 電機工程學系
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