DC 欄位 | 值 | 語言 |
dc.contributor | Dept. of Electr. Eng., National Taiwan Univ. | en |
dc.contributor.author | Tsai, I-Ming | en |
dc.contributor.author | Kuo, Sy-Yen | en |
dc.creator | Tsai, I-Ming; Kuo, Sy-Yen | - |
dc.date | 2001-10 | en |
dc.date.accessioned | 2007-04-19T04:30:44Z | - |
dc.date.accessioned | 2018-07-06T14:19:33Z | - |
dc.date.available | 2007-04-19T04:30:44Z | - |
dc.date.available | 2018-07-06T14:19:33Z | - |
dc.date.issued | 2001-10 | - |
dc.identifier | N/A | en |
dc.identifier.issn | 19449399 | - |
dc.identifier.uri | http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021343 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-57649145355&doi=10.1109%2fNANO.2001.966403&partnerID=40&md5=f784cffe7504baa4cdd143937d0209ee | - |
dc.description.abstract | The discovery of Shor's prime factorization and Grover's fast database search algorithm have made quantum computing the most rapidly expanding research field recently. Nanotechnology, in particular silicon-based nanoscale device, has been proposed as one of the candidates that can be used to implement a quantum computer. In this paper, we have derived a systematic procedure to realize any general m-to-n bit combinational boolean logic using elementary quantum gates. The quantum circuit layout under the locality constraint is then formulated, together with the gate count evaluation function, to reduce the total number of quantum gates required to implement the circuit. © 2001 IEEE. | - |
dc.format | application/pdf | en |
dc.format.extent | 371320 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language | en-US | en |
dc.language.iso | en_US | - |
dc.relation | Nanotechnology, 2001. IEEE-NANO 2001. Proceedings of the 2001 1st IEEE Conference on | en |
dc.relation.ispartof | 1st IEEE Conference on Nanotechnology, IEEE-NANO 2001 | - |
dc.subject.other | Algorithms; Computation theory; Logic circuits; Logic gates; Quantum computers; Quantum electronics; Quantum optics; Quantum theory; Search engines; Database search algorithms; Evaluation function; Nanoscale device; Prime factorization; Quantum Boolean circuits; Quantum circuit; Quantum Computing; Research fields; Nanotechnology | - |
dc.title | Quantum Boolean circuit construction and layout under locality constraint | en |
dc.type | conference paper | en |
dc.identifier.doi | 10.1109/NANO.2001.966403 | en |
dc.identifier.scopus | 2-s2.0-57649145355 | - |
dc.relation.pages | - | - |
dc.identifier.uri.fulltext | http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910021343/1/00966403.pdf | - |
item.fulltext | with fulltext | - |
item.openairetype | conference paper | - |
item.languageiso639-1 | en_US | - |
item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
item.grantfulltext | open | - |
item.cerifentitytype | Publications | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Networking and Multimedia | - |
crisitem.author.dept | Computer Science and Information Engineering | - |
crisitem.author.dept | Center for Quantum Science and Engineering (CQSE) | - |
crisitem.author.orcid | 0000-0002-2504-2608 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電機工程學系
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