https://scholars.lib.ntu.edu.tw/handle/123456789/154734
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, Jai-Ming | en |
dc.contributor.author | YAO-WEN CHANG | en |
dc.contributor.author | Lin, Shih-Ping | en |
dc.creator | Lin, Jai-Ming; Chang, Yao-Wen; Lin, Shih-Ping | - |
dc.date | 2003 | en |
dc.date.accessioned | 2009-02-25T06:57:08Z | - |
dc.date.accessioned | 2018-07-06T15:26:53Z | - |
dc.date.available | 2009-02-25T06:57:08Z | - |
dc.date.available | 2018-07-06T15:26:53Z | - |
dc.date.issued | 2003 | - |
dc.identifier.issn | 10638210 | - |
dc.identifier.uri | http://ntur.lib.ntu.edu.tw//handle/246246/141380 | - |
dc.identifier.uri | http://ntur.lib.ntu.edu.tw/bitstream/246246/141380/1/17.pdf | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-0141750617&doi=10.1109%2fTVLSI.2003.816137&partnerID=40&md5=70eee4a7116d80cd935a89fff8de7786 | - |
dc.description.abstract | Floorplanning/placement allocates a set of modules into a chip so that no two modules overlap and some specified objective is optimized. To facilitate floorplanning/placement, we need to develop an efficient and effective representation to model the geometric relationship among modules. In this paper, we present a P-admissible representation, called corner sequence (CS), for non-slicing floorplans. CS consists of two tuples that denote the packing sequence of modules and the corners to which the modules are placed. CS is very effective and simple for implementation. Also, it supports incremental update during packing. In particular, it induces a generic worst case linear-time packing scheme that can also be applied to other representations. Experimental results show that CS achieves very promising results for a set of commonly used MCNC benchmark circuits. | - |
dc.format | application/pdf | en |
dc.format.extent | 632873 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language | en | en |
dc.language.iso | en_US | - |
dc.relation | IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11 (4): 679-686 | en |
dc.relation.ispartof | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | - |
dc.subject | Floor planning; Layout; Physical design; Placement; VLSI design | - |
dc.subject.other | Graph theory; Mathematical models; Planning; Polynomials; Linear-time packing schemes; VLSI circuits | - |
dc.title | Corner sequence: A P-admissible floorplan representation with a worst-case linear-time packing scheme | en |
dc.type | journal article | en |
dc.identifier.doi | 10.1109/TVLSI.2003.816137 | - |
dc.identifier.scopus | 2-s2.0-0141750617 | - |
item.fulltext | with fulltext | - |
item.grantfulltext | open | - |
dc.relation.pages | 679-686 | - |
dc.relation.journalvolume | 11 | - |
dc.relation.journalissue | 4 | - |
dc.identifier.uri.fulltext | http://ntur.lib.ntu.edu.tw/bitstream/246246/141380/1/17.pdf | - |
item.languageiso639-1 | en_US | - |
item.cerifentitytype | Publications | - |
item.fulltext | with fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.openairetype | journal article | - |
item.grantfulltext | open | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Computer Science and Information Engineering | - |
crisitem.author.dept | Center for Information and Electronics Technologies | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.orcid | 0000-0002-0564-5719 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電機工程學系 |
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