https://scholars.lib.ntu.edu.tw/handle/123456789/154785
標題: | VLSI architecture for forward discrete wavelet transform based on B-spline factorization | 作者: | Huang, Chao-Tsung Tseng, Po-Chih LIANG-GEE CHEN |
關鍵字: | B-spline factorization; Discrete wavelet transform; VLSI architecture | 公開日期: | 2005 | 卷: | 40 | 期: | 3 | 起(迄)頁: | 343-353 | 來源出版物: | Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology | 摘要: | Based on B-spline factorization, a new category of architectures for Discrete Wavelet Transform (DWT) is proposed in this paper. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of the direct implementation or Pascal implementation. And the latter is the part introducing multipliers and can be implemented with the Type-I or Type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could use fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with smaller area and lower speed because only few adders are on the critical path. Three case studies, including the JPEG2000 default (9, 7) filter, the (6, 10) filter, and the (10, 18) filter, are given to demonstrate the efficiency of the proposed architectures. © 2005 Springer Science + Business Media, Inc. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/141446 https://www.scopus.com/inward/record.uri?eid=2-s2.0-17444371286&doi=10.1007%2fs11265-005-5269-z&partnerID=40&md5=a28f89be6e11337241a06f2e712a88cc |
ISSN: | 13875485 | DOI: | 10.1007/s11265-005-5269-z | SDG/關鍵字: | Decomposition; Digital signal processing; FIR filters; Image coding; Image compression; VLSI circuits; B-spline factorization; Discrete wavelet transforms (DWT); Multipliers; VLSI architecture; Wavelet transforms |
顯示於: | 電機工程學系 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。