https://scholars.lib.ntu.edu.tw/handle/123456789/173350
標題: | 適用於超寬頻接收機之互補式金氧半寬頻低雜訊放大器設計與實作 Design and Implementation of CMOS Wideband Low Noise Amplifiers for Ultra Wideband Receiver |
作者: | 陳冠宏 Chen, Kuan-Hung |
關鍵字: | 超寬頻系統;3.1~10.6GHz;串接式雙級分散放大器;寬頻低雜訊放大器;CMOS;3~5GHz;CTDA;UWB;WBLNA;stagger-tuning;current reuse;Ultra wideband | 公開日期: | 2004 | 摘要: | 超寬頻系統將成為無線個人區域網路的通訊技術的主流,雖然超寬頻系統的標準尚未確定,有很多相關研究都將目標放在3.1到10.6GHz間的頻帶。在超寬頻系統的接收機前端所處理的是寬頻訊號,在射頻前端電路需要寬頻低雜訊放大器以提供足夠的增益。本論文實現了二個適用於超寬頻系統接收機射頻前端電路的低雜訊放大器並且使用0.18μm 1P6M CMOS標準製程。第一顆晶片提出串接式雙級分散放大器,此電路的模擬結果在整個3.1到10.6GHz的頻帶提供18dB的增益且輸入及輸出阻抗皆匹配至50Ω,其輸入及輸出回饋損失分別達到-10dB及-9dB以下。這一顆晶片的面積是2.2mm x 1mm 並且在1.8伏的操作電壓下消耗55毫瓦。第二顆晶片實現了一個3到5GHz的低雜訊放大器,此電路使用電流再利用及共振頻率交錯安排的設計技巧,其模擬結果在3到5GHz間達到18dB的增益及低於3dB的雜訊參數,這一顆晶片的面積是1mm x 0.9mm 並且在1.8伏的操作電壓下消耗11.3毫瓦。這兩顆晶片都經過佈局後驗證、實作及量測,其量測結果和模擬結果有相異之處皆以找出原因並經過模擬驗證。 Ultra wideband (UWB) system is the next generation communication technology for wireless personal area networks (WPAN). Although the standard of UWB has not been finalized, many proposed researches target at the band from 3.1 GHz to 10.6GHz. The low noise amplifier (LNA) of UWB RF front-end should possess wideband characteristics. This thesis presents two wideband amplifiers for UWB applications using 0.18μm 1P6M CMOS process. The first chip is a 3.1~10.6GHz CMOS cascaded two-stage distributed amplifier. This circuit using cascaded two-stage topology achieves better gain-bandwidth product performance than the conventional CMOS distributed amplifiers. The simulated gain is 18dB with ±1dB gain flatness over 3.1~10.6GHz bands. Input and output matchings are 50Ω, and the return losses of input and output are below -10dB and -9dB respectively. The power dissipation is 54mW with 1.8V power supply and the chip area is 2.2 x 1mm2. The second chip is a 3~5GHz wideband LNA. This circuit accomplishes low power and wideband characteristics by employing a current reuse structure and arranging the resonant frequencies in stagger. This chip has a gain of 18dB and noise figure less than 3dB over 3~5GHz from post-layout simulation. The power dissipation is 11.3mW with 1.8V power supply and the chip area is 1 x 0.9mm2. All the chips are verified with post-layout simulation and the measurement results of the second chip are also presented. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/57217 | 其他識別: | en-US |
顯示於: | 電子工程學研究所 |
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ntu-93-R91943009-1.pdf | 23.31 kB | Adobe PDF | 檢視/開啟 |
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