https://scholars.lib.ntu.edu.tw/handle/123456789/173383
標題: | 超寬頻收發機互補式金氧半類比前端設計與實作 Design and Implementation of CMOS Analog Front End for Ultra Wideband Transceiver |
作者: | 劉宗德 Liu, Tsung-Te |
關鍵字: | 超寬頻系統;類比前端;延遲鎖定迴路;時脈產生器;接收機;低雜訊放大器;Ultra Wideband (UWB);transceiver;delay-locked loop (DLL);clock generator;low noise amplifier (LNA);analog front end | 公開日期: | 2004 | 摘要: | 由於人們對高速無線通訊的需求,加速推動對於新一代無線通訊系統的開發,而超寬頻系統即為目前新興的無線通訊技術之一。在低成本、低必v消耗以及高系統整合的優勢之下,使用CMOS製程來實現超寬頻接收機為最佳的選擇。本論文探討使用CMOS製程設計與實現兩個位於超寬頻接收機類比前端最重要的電路,分別為低雜訊放大器與時脈產生器電路。 本論文首先會討論低雜訊放大器與時脈產生器電路一般所採用的電路架構以及其設計考量,再進一步提出針對超寬頻系統,使用CMOS製程實現超大型積體電路的硬體電路架構。在低雜訊放大器部分,本論文提出一個不需要任何被動調頻元件,適用於低頻帶超寬頻系統的低必v寬頻CMOS低雜訊放大器。藉著採用共閘級並回授的架構,本低雜訊放大器可以在低必v消耗的情況下達到寬頻的輸入組抗匹配。另外,由於使用電流再利用的技巧,所提出的低雜訊放大器架構可在不消耗多餘必v的情況下輸出更大的增益,並同時減少低雜訊放大器電路對於製程變異的敏感度。在時脈產生器方面,本論文先提出一個具有大操作範圍及適應頻寬特性的延遲鎖定迴路,來實現適用於低頻帶超寬頻系統的低時脈擾動時脈產生器。此延遲鎖定迴路使用數位校正迴路來解決一般常見於大操作範圍延遲鎖定迴路的錯誤鎖定問題,並可進一步加速延遲鎖定迴路的收斂時間。另外,由於使用自我偏壓的技巧,所提出的延遲鎖定迴路架構同時可以適應性的調整頻寬,在大操作範圍及製程、電壓及溫度環境的變異下展現最佳的時脈擾動特性。接下來,本論文提出一個以延遲鎖定迴路為架構,具有低必v消耗、低時脈擾動及大操作範圍特性,適用於超寬頻系統的時脈產生器。利用所提出的數位類比雙迴路適應頻寬延遲鎖定迴路架構,結合互補式的相位偵測性電路,可以確保時脈產生器能在大操作範圍下輸出低時脈擾動的時脈。另外,由於使用自我回授的技巧,可以讓位準轉換器電路降低至少50%的必v消耗。最後,本論文呈現低雜訊放大器與時脈產生器電路晶片的量測結果,藉以驗證所提出電路架構的弁鄐峈穛{。 The desire for high-speed wireless data communication drives the exploration of the emerging wireless technology, Ultra Wideband (UWB). The CMOS technology is the most promising technology for efficient VLSI implementation of a UWB transceiver because of its low cost, low power consumption, and high system level integration. This thesis presents the CMOS design and implementation of the low noise amplifier (LNA) and clock generator circuits, the most critical parts of the analog front end in a UWB transceiver. The general architectures and design issues of the LNA and clock generator circuits will be discussed followed by the CMOS VLSI implementations for UWB system. A low-power wideband CMOS LNA without requiring any passive tuning component for low-band UWB application is first described. The wideband input impedance matching is ensured by employing the common-gate shunt-shunt feedback topology with low power consumption. The current-reuse technique applied in the proposed LNA architecture not only provides additional gain but also reduces the process technology sensitivity of the LNA. Then, a low-jitter clock generator for low-band UWB application based on a wide-range adaptive-bandwidth delay-locked loop (DLL) is presented. The false-locking problem commonly along with the wide-range DLL is eliminated by the digital self-correcting loop which also speeds up the lock-in time of the DLL. With self-biased techniques, the proposed DLL adaptively adjusts bandwidth and exhibits optimal jitter transfer characteristics over a wide frequency range and across process, voltage, and temperature (PVT) variations. A DLL based low-power low-jitter wide-range clock generator for UWB application is also described. The proposed analog-digital dual-loop adaptive-bandwidth structure in conjunction with a complementary phase detector ensures low-jitter clock generation over a wide frequency range. The self-feedback technique reduces the power consumption of the level-shifter circuit 50% at least. Finally, the experimental data for the LNA and the clock generator prototypes are presented to demonstrate the functionalities and performances of the proposed circuit architectures. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/57250 | 其他識別: | en-US |
顯示於: | 電子工程學研究所 |
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ntu-93-R91943006-1.pdf | 23.31 kB | Adobe PDF | 檢視/開啟 |
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