https://scholars.lib.ntu.edu.tw/handle/123456789/173649
標題: | Hole confinement at Si/SiGe heterojunction of strained-Si N and PMOS devices | 作者: | Wei, J.-Y. Maikap, S. Lee, M.H. Lee, C.C. Liu, C.W. |
關鍵字: | MOS C–V;Strain;Device simulation;Hole confinement;Pinning effect | 公開日期: | 2006 | 出版社: | Taipei:National Taiwan University Dept Chem Engn | 卷: | 50 | 期: | 2006 | 起(迄)頁: | - | 來源出版物: | Solid-State Electronics | 摘要: | Due to the Fermi level pinning effect on the hole confinement at the valence band offset, the capacitance–voltage (C–V) characteristics of NMOS capacitor exhibit more obvious plateau than that of PMOS capacitor, demonstrated by both experimental and simulated results. Using device simulation, the ratio of hole density at the oxide/strained-Si interface to that at the strained-Si/relaxed SiGe interface for both N and PMOSFETs is investigated. The much higher hole density ratio in PMOSFETs than that in NMOSFETs also reveals the Fermi level pinning effect. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/2006111501244083 | 其他識別: | 246246/2006111501244083 |
顯示於: | 電子工程學研究所 |
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