https://scholars.lib.ntu.edu.tw/handle/123456789/173660
標題: | Design and Implementation of a Low-Voltage Fast-Switching Mixed-Signal-Controlled Frequency Synthesizer | 作者: | Chiueh, Tzi-Dar Yang, Jin-Bin Wu, Jen-Shi |
關鍵字: | Frequency synthesizer;mixed-signal control;phase-locked loop (PLL) | 公開日期: | 十月-2001 | 出版社: | Taipei:National Taiwan University Dept Mech Engn | 卷: | 48 | 期: | 10 | 起(迄)頁: | 961-971 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | 摘要: | A new frequency synthesizer based on combining the analog phase-locked loop (PLL) and the all digital PLL (ADPLL) is presented. The frequency synthesizer achieves high frequency resolution, broad frequency range, high switching speed, and low supply voltage. The oscillator is controlled by both the digital control word and the control voltage of the analog PLL. It is an array oscillator implemented by symmetric load differential inverting buffers which provide better rejection to supply noise and fabrication variance. Fractional- divider and delay interpolation technique are employed to enhance the divider resolution without inducing jitter. A binary search algorithm is used to find the proper digital frequency control word, which can be saved for later use and greatly speed up the frequency switching process. Fabricated using a 0.6- m SPTM CMOS process, the synthesizer achieves a frequency range of 54–154 MHz with a frequency error less than 1 ppm and a frequency switching time less than 10 s. The chip consumes very little power and draws 47 mW from a 2-V supply voltage. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/200611150121858 http://ntur.lib.ntu.edu.tw/bitstream/246246/200611150121858/1/9306.pdf |
其他識別: | 246246/200611150121858 | DOI: | 10.1109/82.974785 |
顯示於: | 電子工程學研究所 |
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