https://scholars.lib.ntu.edu.tw/handle/123456789/174144
標題: | 超寬頻基頻收發機之設計與實作 Design and Implementation of an Ultra-wideband Baseband Transceiver |
作者: | 楊家驤 Yang, Chia-Hsiang |
關鍵字: | 超寬頻;編碼封包前端;時序飄移;脈波式;符元邊界;規律封包前端;Golay碼;regular preamble;ultra-wideband;timing offset;Golay code;impulse-radio;symbol boundary;coded preamble | 公開日期: | 2004 | 摘要: | 在論文中,針對適用於RF-ID(Radio Frequency Identification)與感測器網路(Sensor network)的短距離、低必v通訊提出一低複雜度的脈波式超寬頻(Ultra-wideband, UWB)基頻收發機架構。由於低必v消耗與低成本目標,在設計階段時我們就將硬體複雜度納入考量,一個由規律封包前端(Regular preamble)、編碼封包前端(Coded preamble)與資料所組成的實體層封包架構被設計用來簡化接收機設計。在規律封包前端階段,相關器組與脈波峰值搜尋器在脈波重覆週期內負責找出脈波精確位置;在編碼封包前端階段,Golay碼匹配濾波器與符元邊界偵測器共同運作來尋找符元邊界;到了資料階段,資料回復電路透過相關器直接回復資料。另外,接收機還包括由早遲迴路所構成的時序回復電路以克服發射與接收機間取樣頻率誤差所造成的時序飄移。模擬結果顯示所提出的收發機架構在真實多重路徑通道下運作良好。數種低必v技巧從架構層級至電路層級被用於電路設計中,最後晶片面積約為1.6 x 1.7 mm2使用UMC 0.18 um 1P6M CMOS製程,佈局後模擬結果顯示晶片核心必v消耗為13mW,操作於62.5MHz,核心電壓1.8-V。 In this work, we propose a low-complexity transceiver architecture for impulse-radio ultra-wideband (UWB) communication that focuses on short range, low power applications such as radio frequency identification (RF-ID) and sensor network. Since power and cost are the main design issues, hardware simplicity is taken into account early in the design stage. A physical-layer packet format made up of regular preamble, coded preamble and data is proposed to facilitate receiver design. In the regular preamble stage, a bank of correlators and a peak searcher are responsible for finding the exact pulse position within a pulse repetition interval. During the coded preamble stage, a Golay code matched filter and a symbol boundary detector work together to search for the symbol boundary. Finally, a data recovery block recovers the data using a correlator. In addition, the receiver includes an early-late timing tracking loop that can overcome timing offset between the receiver clock and the received signal. Simulation results show that the transceiver functions as expected in realistic multipath channels. Several low-power techniques from architectural level to circuit level have been applied in circuit design. The final receiver chip is designed in a 0.18 um CMOS process and its die size is about 1.6 x 1.7 mm2. Post-layout simulation shows that the receiver chip’s core power consumption is 13mW when it operates at 62.5MHz clock rate from a 1.8-V supply voltage. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/57453 | 其他識別: | zh-TW |
顯示於: | 電子工程學研究所 |
檔案 | 描述 | 大小 | 格式 | |
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ntu-93-R91943002-1.pdf | 23.31 kB | Adobe PDF | 檢視/開啟 |
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