https://scholars.lib.ntu.edu.tw/handle/123456789/174364
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor | 郭正邦 | en |
dc.contributor | 臺灣大學:電子工程學研究所 | zh_TW |
dc.contributor.author | 許家豪 | zh |
dc.contributor.author | Hsu, Chia-Hao | en |
dc.creator | 許家豪 | zh |
dc.creator | Hsu, Chia-Hao | en |
dc.date | 2005 | en |
dc.date.accessioned | 2007-11-27T07:09:18Z | - |
dc.date.accessioned | 2018-07-10T01:32:59Z | - |
dc.date.available | 2007-11-27T07:09:18Z | - |
dc.date.available | 2018-07-10T01:32:59Z | - |
dc.date.issued | 2005 | - |
dc.identifier | zh-TW | en |
dc.identifier.uri | http://ntur.lib.ntu.edu.tw//handle/246246/57600 | - |
dc.description.abstract | 本論文中提出了雙閘全解離絕緣體上矽金氧半元件當上下閘極分別為N+/P+時轉折電壓與汲極電流的分析。 第二章說明一般在閘極對稱情形下,雙閘全解離絕緣體上矽金氧半元件的臨界電壓模型,並考慮不同通道長度的情形。 第三章中討論雙閘全解離絕緣體上矽金氧半元件當上下閘極為N+ / P+多晶矽時,轉折電壓的模型,並藉由二維元件模擬軟體(MEDICI)驗證之。 第四章中討論雙閘全解離絕緣體上矽金氧半元件當上下閘極為N+ / P+多晶矽時,汲極電流的模型,並藉由二維元件模擬軟體(MEDICI)驗證之。 | zh_TW |
dc.description.abstract | This thesis reports an analysis of double-gate SOI CMOS devices using top N+/Bottom P+ poly gate structure. In chapter 2, we discuss the threshold voltage model of the normal DG FD SOI PMOS devices without considering gate misalignment effect in different channel length. In chapter 3,we report an analytical short-channel effect (SCE) transition voltage model of double-gate (DG) fully-depleted (FD) SOI NMOS devices with the n+/p+ polysilicon top/bottom gate. The existence of the transition voltage is due to the simultaneous turn-on of the bottom channel in addition to the top channel. As verified by 2D simulation results, this analytical transition voltage model provides a well prediction of the SCE transition voltage behavior of the devices. In chapter 4, we report an analytical drain current model of double-gate (DG) fully-depleted (FD) SOI NMOS devices with the n+/p+ poly top/bottom gate considering the threshold/transition voltage effects. Via a comprehensive current conduction mechanism model, the analytical drain current model considering the threshold/transition voltage effects could provide an accurate prediction of performance the 100nm DG FD SOI NMOS device with the n+/p+ poly top/bottom gate as verified by the 2D simulation results. | en |
dc.description.tableofcontents | 第一章 導論 1.1 SOI元件的簡介………………………………………...1 1.2 DG FD SOI 元件的發展…………………………….....2 1.3 DG FD SOI 元件的結構與製程…………………….....3 1.4 DG FD SOI 元件的問題與優點……………………….6 1.5 本論文目標……………………………………………..7 第二章 雙閘全解離絕緣體上矽金氧半元件,臨界電壓之模型推導 2.1 簡介…………………………………………………….8 2.2 臨界電壓模型推導…………………………………….9 2.3 臨界電壓模型驗證…………………………………….15 2.4 結論…………………………………………………….16 第三章 雙閘全解離絕緣體上矽金氧半元件當上下閘極為N+ / P+多晶矽時,轉折電壓模型 3.1 簡介………………………………………………………19 3.2 轉折電壓模型推導………………………………………22 3.3 轉折電壓模型驗證………………………………………27 3.4 N+/P+與N+/N+雙閘式元件的比較……………………..33 3.5 結論………………………………………………………40 第四章 雙閘全解離絕緣體上矽金氧半元件當上下閘極為N+ / P+多晶矽時,電流模型 4.1 簡介………………………………………………………41 4.2 汲極電流模型推導………………………………………47 4.2.1 飽和電壓的推導..........................................................47 4.2.2 電流及通道調變效應的推導........................................ 48 4.3 汲極電流模型驗證………………………………………56 4.4 N+/P+與N+/N+雙閘式元件的比較……………………..59 4.5 結論 ……………………………………………………..64 第五章 總結…………………………………………………….65 參考文獻……………………………………………………………...66 | zh_TW |
dc.language | zh-TW | en |
dc.language.iso | en_US | - |
dc.subject | 雙閘式 | en |
dc.subject | 絕緣體上矽金氧半元件 | en |
dc.subject | Double-Gate | en |
dc.subject | soi | en |
dc.title | 雙閘式絕緣體上矽金氧半元件當上閘極為N+/ 下閘極為P+多晶矽時的分析 | zh |
dc.title | Analysis of Double-Gate SOI CMOS Devices Using Top N+/Bottom P+ Poly Gate Structure. | en |
dc.type | thesis | en |
dc.relation.reference | 第一章 [1.1] James B. Kuo and S. C. Lin, “Low-Voltage SOI CMOS VLSI Devices and Circuits” New York: Wiley, ISBN 0471417777, 2001. [1.2] James B. Kuo and K. W. Su, “CMOS VLSI Engineering: Silicon-on-Insulator (SOI)” Kluwer Academic: Dordrecht, 1998. [1.3] D. Hisamoto, "FD/DG-SOI MOSFET," IEDM Dig. pp. 429-432, 2001. [1.4] A. Vandooren, S. Cristoloveanu, and J. Colinge, "The Dynamic Conductance and Transconductance in Double-Gate (Gate-All-Around) SOI Devices," Dig. SOI Conf. pp. 116-117, Oct. 2000. [1.5] D. Esseni, M. Mastrapasqua, C. Fiegna, G. Celler, L. Selmi and E. Sangiorgi, "An Experimental Study of Low Field Electron Mobility in Double-Gate, Ultra-thin SOI MOSFETs," IEDM Dig. pp. 445-448, 2001. [1.6] B. Yu, T. Tanaga, and C. Hu, "Modeling Off-State Leakage Current of DG-SOI MOSFETs for Low-Voltage Design," SOI Conf. Dig. pp. 15-16, 1996. [1.7] K. Takeuchi, R. Koh, and T. Mogami, "A Study of the Threshold Voltage Variation for Ultra-Small Bulk and SOI CMOS," IEEE Trans. Elec. Devices, Vol. 48, No. 9, pp. 1995-2001, Sept. 2001. [1.8] J. P. Colinge, M. H. Gao, and A. Romano, “Silicon-on-Insulator “Gate-All-Around” MOS Device,” IEEE SOS/SOI Technology Conference, pp. 137-138, 1990. [1.9] F. Allibert, M. Vinet, and J.Lolivier, “Characterization of Ultra-Thin SOI Films for Double-Gate MOSFETs,” IEEE Int. SOI Conf., pp. 187-188, 2002. [1.10] R. Zhang and K. Roy, “Low-Power High-Performance Double-Gate Fully Depleted SOI Circuit Design,” IEEE Trans. Elec. Devices, Vol. 49, No. 5, pp. 852-862, May 2002. [1.11] J. M. Hergenrother et al., “50nm Vertical Replacement-Gate (VRG) nMOSFET with ALD HfO2 and Al2O3 Gate Dielectrics,” IEDM Tech. Dig., pp. 51-54, 2001. [1.12] J. H. Lee, et al., “ Super Self-Aligned Double-Gate (SSDG) MOSFETs Utilizing Oxidation Rate Difference and Selective Epitaxy,” IEDM Tech. Dig., pp. 71-74, 1999. 第二章 [2.1] P. Francis, A. Terao, D. Flandre, and F. V. de Wiele, "Modeling of Ultrathin Double-Gate nMOS/SOI Transistors," IEEE Trans. Electron Devices, Vol. 41, No. 5, pp. 715-720, May 1994. [2.2] K. W. and J. B. Kuo, "A Non-Local Impact Ionization/Lattice Temperature Model for VLSI Double-Gate Ultrathin SOI NMOS Devices," IEEE Trans. Electron Devices, Vol. 44, No. 2, pp. 324-330, Feb. 1997. [2.3] K. Suzuki, Y. Tosaka, and T.Sugii, “Analytical Threshold Voltage Model for Short Channel Effect n+ -p+ Double-Gate SOI MOSFET’s,” IEEE Trans. Electron Devices, Vol. 43, No. 5, pp. 732-738, May 1996. [2.4] S. Chen and J. Kuo, "Deep Submicrometer Double-Gate Fully-Depleted SOI PMOS Devices: a Concise Short-Channel Effect Threshold Voltage Model Using a Quasi-2D Approach," IEEE Trans. Elec. Dev., Vol. 43, No. 9, pp. 1387-1393, Sept. 1996. [2.5] K. K. Young, “Short Channel Effect in Fully Depleted SOI MOSFET’s, ” IEEE Trans. Elec. Dev., Vol. ED-36, No. 2, pp. 399-402, Feb. 1989. [2.6] V. Aggarwal, M. K. Khanna, and R. Sood, “Analytical Two-Dimensional Modeling for Potential Distribution and Threshold Voltage of the Short-Channel Fully Depleted SOI (Silicon-on-Insulator) MOSFET’s” Solid State Electron., vol. 37, no. 8, pp. 1537-1542, 1994. [2.7] R. H. Yan, A. Qurmazd, and K. F. Lee, “Scaling the Si MOSFET: From Bulk to SOI to Bulk,” IEEE Trans. Elec. Dev., Vol. 39, No. 7, pp. 1704-1710, 1992. 第三章 [3.1] J. B. Kuo et al, “Low-Voltage SOI CMOS Devices and Circuits,” Wiley, New York, 2001. [3.2] R. H. Yan, A. Ourmazd, K. F. Lee, “Scaling the Si MOSFET: From Bulk to SOI to Bulk,” IEEE Trans. Electron Devices, Vol. 39, No. 7, pp. 1704-1710, July 1992. [3.3] P. Francis, A. Terao, F. Van de Wiele,” Modeling of Ultrahtin Double-Gate nMOS/SOI Transistors,” IEEE Trans. Electron Devices, Vol. 41, No. 5, pp.715-720, May 1994. [3.4] S. S. Chen and J. B. Kuo, “Deep Submicrometer Double-Gate Fully-Depleted SOI PMOS Devices: A Concise Short-Channel Effect Threshold Voltage Model Using a Quasi-2D Approach,” IEEE Trans. Electron Devices, Vol. 43, No. 9, pp. 1387-1393, Sept 1996. [3.5] K. Suzuki and T. Sugii, “Analytical Model for n+-p+ Double-Gate SOI MOSFET’s,” IEEE Trans. Electron Devices, Vol. 42, NO. 11, pp. 1940-1948, Nov. 1995. [3.6] K. Suzuki, Y. Tosaka, and T. Sugii, “Analytical Threshold Voltage for Short Channel n+-p+ Double-Gate SOI MOSFET’s,” IEEE Trans. Electron Devices, Vol. 43, No. 5, pp. 732-738, May 1996. 第四章 [4.1]CAD Model for Threshold and Subthreshold Conduction in MOSFET's P. Antognetti,D.D. Caviglia and E. Profumo,IEEE J. Solid-State Circuits,Vol.17,No.3,pp. 454-458,Jun.1982 [4.2]An analytical drain current model considering both electron and lattice temperatures simultaneously for deep submicron Ultrathin SOI NMOS Devices with self-heating Yu-Guang Chen;Shyh-Yih Ma;James B. Kuo;Zhiping Yu;Robert W. Duttin IEEE Transcations on Electron Device,VOL. 42,NO.5,pp.899-906,May 1995 [4.3]A non-local impact ionization/lattice temperature model for VLSI double-gate ultrathin SOI NMOS devices Ker-Wie Su; Kuo, J.B.;Electron Devices, IEEE Transactions on Volume 44, Issue 2, Feb. 1997 Page(s):324 - 330 [4.4]Analysis of Current Conduction in Short-Channel Accumulation-Mode SOI PMOS Device Ker-Wei Su and James B. Kuo IEEE Transactions On Electron Device. Vol. 44.No.5.May 1997 pp.832-840 [4.5]Y. A. El-Mansy and A. R. Boothroyd, A simple two-dimensional model for IGFET operation in the saturation region, IEEE Trans. Electron Devices,vol.24 ,no.3 ,pp.254-262,Mar.1987 [4.6]H. C. Chow, W. S. Feng, and J. B. Kuo, An improved analytical short-channel MOSFET model valid in all regions of operation for analog/digital circuit simulation,IEEE Trans, CAD of IC,col.11 no.12,pp. 1522-1528,Dec.1992. [4.7]K. Mayaram, J. C. Lee, and C.Hu, Amodel for the electric field in lightly doped drain structures, IEEE Trans. Electron Devices, vol.34,no. 7,pp. 1509-1518,July 1987 [4.8]H.-K. Lim and J. G. Fossum. Current-voltage characteristics of thin-film SOI MOSFET’s in strong inversion, IEEE Trans. Electron Devices, vol.31,no. 4,pp. 401-408, 1984 [4.9]R.-H. Yan, A. Ourmazd, and K. F. Lee,Scaling the Si MOSFET:From bulk to SOI to bulk,IEEE Trans.Electron Devices, vol. 37,no. 7,pp.1740-1710, 1992. | en |
item.fulltext | no fulltext | - |
item.languageiso639-1 | en_US | - |
item.openairecristype | http://purl.org/coar/resource_type/c_46ec | - |
item.cerifentitytype | Publications | - |
item.openairetype | thesis | - |
item.grantfulltext | none | - |
顯示於: | 電子工程學研究所 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。