https://scholars.lib.ntu.edu.tw/handle/123456789/174390
標題: | 具快速選頻機制之10 GHz CMOS 頻率合成器 A 10-GHz CMOS Frequency Synthesizer with an Agile VCO Calibration |
作者: | 賴宥任 Lai, Yu-Jen |
關鍵字: | 選頻;鎖相迴路;頻率合成器;calibration;PLL;frequency synthesizer | 公開日期: | 2005 | 摘要: | 隨著網路的普及以及各種通訊應用的蓬勃發展,對於頻寬及資料傳輸速度的要求也越來越高,許多有線及無線通訊系統也因此朝高頻的方向發展。本研究即針對這一趨勢,發展了一個操作在10 GHz的頻率產生器(Frequency Synthesizer),此一電路可應用於10 GHz乙太網路、無線通訊、光纖通訊等高速通訊系統上。為了達到低成本的目的,我們選擇使用CMOS製程來設計及實現,並且提出了新的系統及電路架構,以達到高效能的設計目標。 傳統的鎖相迴路(PLL)型頻率產生器,為了涵蓋足夠的頻率範圍,設計時一般會有VCO Gain (KVCO, MHz/V)過大的缺點,進而影響了Phase Noise及Spurs等重要效能,這一問題通常可以藉由將VCO的頻率曲線(Tuning Curves)分段(Discrete Tuning)而得到改善。此一方法必須搭配一個VCO頻率選取校正電路來自動選取最適當的VCO頻率曲線。現有的VCO頻率選取校正架構一般可分為閉迴路及開迴路兩大類,它們各有其優缺點,但共同的問題為校正耗時長,進而限制了有效的通訊傳輸率。本研究首先針對這一問題加以研究,並且提出了一個快速的VCO校正電路架構(VCO Calibration)。 在進行VCO頻率校正時,PLL為開迴路(Open Loop)的狀態,等到校正完成再進入閉迴路(Close Loop)狀態做頻率鎖定的動作。與傳統的開迴路校正方式不同的是,此校正電路乃是藉由FREF及FVCO/N週期長短的比較來決定如何從一組VCO Tuning Curves中選取最適當的一條曲線。 在電路實現上,二個待比較信號(FREF及FVCO/N)分別接上除二電路以得到50% Duty Cycle,除二電路輸出信號的Pulse寬度即為原信號之週期。在進行比較時,將二信號之正緣(Rising Edge)時間差透過Charge Pump對一電容進行放電之動作,接著利用二信號之負緣(Falling Edge)時間差進行充電之動作,所得到的淨電壓變化量即為二信號之週期差,此週期差即為VCO頻率選取校正的依據。為了能自動取得最適當的信號相位以提高比較之精確度,本研究進一步提出了Phase Selector等混合信號電路 (Mixed-Mode Circuit)架構,並利用Phase Selector的特性來避免Charge Pump Dead Zone的產生。由於此VCO頻率選取校正是依據週期的比較而來,因此完成校正所須的時間甚短,相較於其它現有的架構,本研究提出的方法節省了許多寶貴的通訊時間。 本研究的另一創新為提出了利用可程式電阻陣列(Programmable Switched Triode Transistor Array)來取代傳統VCO的電流鏡(Tail Current Source)偏壓方式,此一方法可降低偏壓電晶體所造成的相位雜訊效應,同時可降低面積與增進效能。 此一10-GHz CMOS Frequency Synthesizer 是利用TSMC 0.18 micro-meter 製程來實現,並已取得實際量測結果。所有電路包括VCO、PLL、Calibration Circuits、及Loop Filter等均已整合於晶片之內。 Owing to the popularity of various networking and communication applications, the demands on wide bandwidth and high data rate grow stronger. Many wireless/wireline communication systems are therefore moving towards higher operating frequencies. To meet this trend, this research has developed a 10-GHz frequency synthesizer, which can be applied to a 10-G Ethernet, wireless, or fiber optic applications. In order to achieve low-cost design goal, CMOS technology has been selected to implement this design. Furthermore, novel system and circuit architectures are also proposed to attain high performance. For a conventional phase-locked loop (PLL) type frequency synthesizer, the voltage-controlled oscillator (VCO) gain (KVCO, MHz/V) must be designed to be large enough in order to cover a wide frequency tuning range. This, however, degrades the phase noise and spurs performance. This issue can be alleviated by breaking a continuous wide-range tuning curve into several narrower curves with sufficient frequency overlap. It is typically achieved by employing a switched capacitor array in the LC-VCO to implement such discrete tuning. This method requires a VCO calibration circuit to search for the proper curve. In general, the VCO calibration can be categorized into closed- and opened-loop approaches. Both have advantages and disadvantages. However, one common issue is that they both require considerable amount of time to complete the calibration task, therefore wasting precious communication time. This work first addresses this issue and proposes a novel agile VCO calibration architecture. During the calibration, the PLL loop is opened. Once the calibration is completed, the PLL loop will then close and lock to the desired channel frequency. The major difference between this approach proposed here and the conventional one is that this method performs the calibration by comparing the length of periods of FREF and FVCO/N, rather than counting cycles. For the circuit implementation, there two signals (FREF and FVCO/N) are first divided by two in frequency, such that the output pulse widths represent their signal periods. During comparison, the phase difference of the rising edges of these two signals (now FREF/2 and FVCO/2N) discharges a capacitor; while the phase difference of the falling edges of FREF/2 and FVCO/2N charges the same capacitor. The net voltage change across the capacitor is a representative of the period difference between these two signals, and is based upon to select the propose VCO tuning curve (VCO calibration). In order to enhance the accuracy of the proposed architecture, various mixed-mode circuits, such as Phase Selector, are also proposed and developed. Due to the nature of this calibration approach (comparing signal periods rather than counting signal cycles), the calibration can be completed in just a few cycles, therefore it is much faster than the conventional ones (both closed- and opened-loop methods). From the communication point of view, this allows more time spending on the data transmission/reception, increasing actual data throughput. Another circuit innovation of this work is in the VCO biasing technique. Conventional current source tends to contribute phase noise to the VCO output significantly. Here, the VCO is biased with a programmable switched transistor array to alleviate this issue. From the simulation, this approach also requires less area for a given performance. This 10-GHz CMOS frequency synthesizer has been fabricated in TSMC 0.18 micro-meter technology. This chip has been measured. All circuit components, including the VCO, PLL, Loop Filter, and the calibration circuit have been integrated into the single chip. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/57626 | 其他識別: | en-US |
顯示於: | 電子工程學研究所 |
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ntu-94-R92943097-1.pdf | 23.31 kB | Adobe PDF | 檢視/開啟 |
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