https://scholars.lib.ntu.edu.tw/handle/123456789/174394
標題: | 以統計模擬方法對類比數位轉換器內建自我測試電路之效能評估 Evaluation of an ADC BIST Technique Using Statistical Simulation |
作者: | 陳奕任 Chen, Yi-Ren |
關鍵字: | 統計模擬;內建自我測試電路;效能評估;Evaluation;Statistical Simulation;BIST | 公開日期: | 2004 | 摘要: | 類比/混模訊號設計測試電路技術仍然不像數位的技術一般被大多採用,其中一個原因是缺乏有效方法來評估它的可信效率。本論文開發了一個製程統計模擬工具來評估類比/混模訊號設計測試電路技術的規格輸出表現分佈。不同於傳統製程參數不相關且與參數獨立的蒙地卡羅模擬方法,本模擬採用參數有相關性而產生更實際的變數來估計,並實現在一個快閃式類比數位轉換器內建自測電路以證實其效率。評估這一個電路技術結果顯示出,此簡易快閃式高速類比數位轉換器電路架構易受製程漂移影響,靜態的內建自測電路架構適合測試靜態規格,而不適於測試動態規格。 Unlike their digital counterparts, analog/mixed-signal DfT (Design-for-Test) techniques are still far from being widely adopted. One of the reasons that lead to the low acceptance is the lack of efficient methodologies to evaluate the effectiveness of the AMS (analog/mixed-signal) DfT techniques. In this thesis, we developed a statistical process simulation tool to estimate the performance distribution of an AMS circuit. Unlike traditional Monte-Carlo simulation techniques which disregard the correlation between process and circuit parameters, the proposed statistical simulation tool takes into account the dependency and thus generates a more realistic estimation. The statistical simulation tool is applied to an ADC BIST technique to validate the effectiveness. The results demonstrated that the simple high speed flash ADC is sensitive to process variation, and the static BIST technique is suitable for testing static specifications but not dynamic specifications. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/57630 | 其他識別: | en-US |
顯示於: | 電子工程學研究所 |
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ntu-93-R91943087-1.pdf | 23.31 kB | Adobe PDF | 檢視/開啟 |
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