https://scholars.lib.ntu.edu.tw/handle/123456789/174631
標題: | 依序輸出入且節省記憶體之快速傅立葉轉換架構設計 Ordered Input-Output and Memory-Aware FFT Architecture Design |
作者: | 劉淑敏 Liu, Shu-Min |
關鍵字: | 傅立葉;記憶體;架構;Memory-based;FFT | 公開日期: | 2009 | 摘要: | 快速傅利葉轉換處理器一直為影像處理以及通訊系統所廣泛使用,截至目前為止每年仍有許多關於快速傅利葉轉換處理器的研究不斷地進行與發表,意味著對於提升快速傅利葉轉換處理器各方面功能之需求不曾中斷,因此如何增進效能以及減少硬體資源為快速傅利葉轉換處理器的最大課題。於快速傅利葉轉換運算後的結果為位元反向順序的輸出序列,這並不適合用於快速傅利葉轉換的一些應用如正交分頻多工系統,本論文提出了一種節省記憶體快速傅利葉轉換處理器的新式架構與設計方法,能夠不需經由額外的位元翻轉(bit-reversed)電路亦可產生最佳輸出資料之順序,此架構對於那些要求快速傅利葉轉換器處理連續輸入的資料序列循序輸出的系統來說,是非常合適的設計架構。 Fast Fourier transform (FFT) processors have been widely used in image processing as well as in communication systems. Up to date, many researches about FFT are being carried on and unceasingly got published every year. It signifies that the demand on how to improve the computation speed never stop. Also, trade-off between the performance and hardware resources of an FFT design becomes an important issue. typical FFT operation transforms an in-order input sequence into an output sequence in bit reverse order, which is not suitable to use in some application like orthogonal frequency division multiplexing (OFDM). This work proposed a novel memory-based FFT architecture which has the property that both inputs and outputs are addressed in natural order without a bit-reversed electric circuit. It is very suitable for those systems where the continuous data sequences that call for the FFT processing enter and exit from the system sample by sample sequentially. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/189154 |
顯示於: | 電子工程學研究所 |
檔案 | 描述 | 大小 | 格式 | |
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ntu-98-P96943002-1.pdf | 23.32 kB | Adobe PDF | 檢視/開啟 |
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